1. Field of the Invention
This invention relates to an information processing device for efficiently performing routine and non-routine processing for routine data and general non-routine processing, and an entertainment system, such as a home game machine, employing the information processing device.
2. Description of Related Art
In a computer system, such as a workstation or a personal computer, or an entertainment system, such as a video game machine, attempts have been made for increasing the CPU speed and for enhancement of a cache memory system, adoption of parallel computing functions and introduction of a dedicated calculating system, for coping with the increased processing volume and the increased data volume.
In particular, enhancement of the cache memory system and parallel calculations (so-called multi-media commands) have been prevalent in the personal computer.
Although enhancement to the cache memory is statistically meritorious for so-called general-purpose processing, such as non-routine processing, the conventional cache structure cannot be said to be efficient for routine processing represented by e.g., MPEG decoding executed by a parallel calculation command, that is DSP type processing for large-capacity data.
That is, with the DSP processing of large-capacity data, flowing data is hardly accessed again. Therefore, a memory structure which is increased in speed on second accessing, such as a cache memory, cannot be said to be effective. The data accessed many times with the above DSP processing is temporary data of the internal parameters and the inner work area. The cache structure in which data used only once is necessarily written in the main memory cannot be said to be efficient.
Since the data format is fixed in this routine processing, a suitable data volume that is read into the cache can be set. However, since the data volume read at a time cannot be controlled by a program in the usual cache structure, data transfer cannot be increased in efficiency.
Also, if a dedicated calculating device for routine processing is used, there are occasions wherein data transfer to the dedicated calculating device represents a bottleneck in processing, although the device is high in processing speed and in efficiency for routine processing. Even if the processing bottleneck in data transfer is eliminated by employing a direct memory address (DMA) or providing a dedicated bus, the device is difficult to control from the main program and only poor in flexibility.
It is therefore an object of the present invention to provide an information processing device and an entertainment system for efficiently performing various processing operations, such as routine and non-routine processing for routine data and general non-routine processing.
In one aspect, the present invention provides an information processing apparatus including a main processor unit at least including parallel computational processing means, cache storage means, and direct-memory-accessible internal high-speed storage means, main storage means and a direct memory accessing controlling unit for direct memory access transfer control between the internal high-speed storage means in the main processor unit and the main storage means. The main processor unit, main storage means and the direct memory accessing unit are interconnected over a main bus.
Preferably, a floating decimal point vector processing unit at least including vector processing means and a direct-memory-accessible internal high-speed storage means is provided on the main bus.
In another aspect, the present invention provides an information processing apparatus including a main processor unit at least including computational processing means and cache storage means, main storage means, a floating decimal point vector processing unit at least including vector processing means and direct-memory-accessible internal high-speed storage means, and a direct memory accessing control unit for direct-memory-access transfer control between the internal high-speed storage means in the vector processor unit and the main storage means. The main processor unit, main storage means and the direct memory accessing control unit are interconnected over a main bus.
Preferably, the floating decimal point vector processing unit is made up of a first vector processor and a second processor and the first vector processor is tightly connected to the main processor unit to form a co-processor.
In an entertainment system according to yet another aspect of the present invention, the above-described information processing apparatus is a main processor system, to which is connected, via a sub-bus interface, a sub-processor system comprised of the sub-processor, sub-storage means and a sub-DMAC over a sub-bus. To this sub-bus are connected reproducing means for an external storage means, such as a CD-ROM drive, and actuating means such as a manual controller.
According to the present invention, since direct-memory-accessing transfer control is performed by a DMA controller between main storage means and the internal high-speed storage means of the main processing unit having, besides the parallel computational processing means, parallel computational processing means and the cache storage means, routine processing, in particular the processing of integer routine data, can be performed efficiently.
By additionally providing a floating decimal point vector processing unit having at least one direct memory-accessible high-speed internal storage means and vector computational processing means, routine processing of routine data can be performed efficiently. By providing two such floating decimal point vector processing unit and by tightly connecting one of the vector processors to the main processing unit for use as a co-processor, non-routine processing of routine data can be performed efficiently, while routine processing of routine data can be performed efficiently by the remaining vector processor.
By having, in addition to the main processing unit having usual cache storage means effective for non-routine processing, a vector processor having a high-speed internal memory and a data transfer mechanism by DMA suited to routine processing of routine data, and a tightly connected vector co-processor having a high-speed internal memory and a data transfer mechanism by DMA suited to non-routine processing of routine data, high-efficiency processing can be realized for a variety of processing configurations.
Moreover, by providing, in addition to the main processing unit having direct memory accessible internal high-speed memory means suited for routine processing and usual cache storage means effective for non-routine processing, a vector processor having a high-speed internal memory and a data transfer mechanism by DMA suited to routine processing of routine data and a high-speed internal memory and a direct memory accessing mechanism for direct memory accessing between the high-speed internal storage means in the vector processor and the high-speed internal memory in the vector processor, non-routine processing and routine and non-routine processing for routine data can be performed efficiently.